Marvin Onabajo's Analog Circuit Design for Process Variation-Resilient PDF

By Marvin Onabajo

ISBN-10: 1461422957

ISBN-13: 9781461422952

This ebook describes a number of strategies to deal with variation-related layout demanding situations for analog blocks in mixed-signal systems-on-chip. The tools provided are effects from contemporary learn works related to receiver front-end circuits, baseband filter out linearization, and information conversion. those circuit-level concepts are defined, with their relationships to rising system-level calibration ways, to song the performances of analog circuits with electronic information or regulate. assurance additionally incorporates a technique to make the most of on-chip temperature sensors to degree the sign strength and linearity features of analog/RF circuits, as verified by means of try out chip measurements.

  • Describes various variation-tolerant analog circuit layout examples, together with from RF front-ends, high-performance ADCs and baseband filters;
  • Includes integrated trying out innovations, associated with present commercial trends;
  • Balances digitally-assisted functionality tuning with analog functionality tuning and mismatch relief approaches;
  • Describes theoretical thoughts in addition to experimental effects for attempt chips designed with variation-aware techniques.

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Additional resources for Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip

Example text

Conversely, calibration could also be performed by monitoring the bit error rate (BER) in the DSP from processing a special test sequence or customary pilot symbols at the beginning of receptions. Since linearity degradation impacts the BER, such a calibration could be computationally more efficient than calculating and analyzing the fast Fourier transform in the DSP. Regardless of the specific digital calibration algorithm, the digitally-controlled correction capability of the attenuation-predistortion linearization scheme can potentially enable filter linearity tuning in integrated receiver applications without the need for extra DACs.

Narendra, Y. Hoskote, H. Wilson, C. Lam, M. Shuman, C. Tokunaga, D. Somasekhar, S. Tang, D. Finan, T. Karnik, N. Borkar, N. Kurd, V. De, Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging, in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb 2007, pp. 292–604 46. -C. Lin, K. Banerjee, A design-specific and thermally-aware methodology for trading-off power and performance in leakage-dominant CMOS technologies.

Manuf. 21(4), 585–591 (2008) 7. A. Zivkovic, F. van der Heyden, G. Gronthoud, F. de Jong, Analog test bus infrastructure for RF/AMS modules in core-based design, in Proceedings of 13th European Test Symposium, May 2008, pp. 27–32 28 2 Process Variation Challenges and Solutions Approaches 8. K. Agarwal, J. Hayes, S. Nassif, Fast characterization of threshold voltage fluctuation in MOS devices. IEEE Trans. Semicond Manuf. 21(4), 526–533 (2008) 9. F. Glas, Digital I/Q imbalance compensation in a low-IF receiver, in Proceedings of IEEE Global Telecommunications Conference (GLOBECOM), vol.

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Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip by Marvin Onabajo

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